DCJ11

 

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KDJ11-D/S
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DCJ11

 

The DCJ11-data sheet can be found at http://www.bitsavers.org/pdf/dec/pdp11/1173/EK-DCJ11-UG-PRE_J11ug_Oct83.pdf

 I found this on Jonathan Bowen's Microprocessor instruction set cards page. I inserted the pin descriptions from the KDJ11-D/S manual.

----------------------------------------------------------------
|                                                              |
|                                                              |
|                Digital Equipment Corporation                 |
|                                                              |
|                   JJJJJJJ       1     1                      |
|                      J         11    11                      |
|                      J          1     1                      |
|                      J    XXX   1     1                      |
|                      J          1     1                      |
|                  J   J          1     1                      |
|                   JJJ          111   111                     |
|                                                              |
|         J-11 MICROPROCESSOR Instruction Set Summary          |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                    _________    _________                    |
|                   |         \__/         |                   |
|        --> TEST1 -|1                   60|- DAL6 <-->        |
|         <-- AIO0 -|2                   59|- DAL7 <-->        |
|         <-- AIO1 -|3                   58|- DAL8 <-->        |
|         <-- AIO2 -|4                   57|- DAL0 <-->        |
|         <-- AIO3 -|5    ____________   56|- DAL9 <-->        |
|         --> PWRF -|6   |            |  55|- DAL10 <-->       |
|          --> FPE -|7   |Control chip|  54|- DAL11 <-->       |
|        --> EVENT -|8   |____________|  53|- DAL12 <-->       |
|         --> HALT -|9                   52|- DAL13 <-->       |
|         --> IRQ0 -|10                  51|- DAL14 <-->       |
|         --> IRQ1 -|11                  50|- DAL15 <-->       |
|         --> IRQ2 -|12                  49|- DAL1 <-->        |
|         --> IRQ3 -|13                  48|- DAL2 <-->        |
|       --> PARITY -|14                  47|- DAL3 <-->        |
|              GND -|15       DCJ11      46|- Vcc              |
|              Vcc -|16                  45|- GND              |
|          <-- BS0 -|17                  44|- DAL4 <-->        |
|          <-- BS1 -|18                  43|- DAL5 <-->        |
|          <-- MAP -|19                  42|- DV <--           |
|       <--> ABORT -|20                  41|- BUFCTL -->       |
|        <-- DAL21 -|21                  40|- ALE -->          |
|        <-- DAL20 -|22                  39|- STRB -->         |
|        <-- DAL19 -|23   ____________   38|- SCTL -->         |
|        <-- DAL18 -|24  |            |  37|- XTAL0 <-->       |
|        <-- DAL17 -|25  | Data  chip |  36|- XTAL1 <-->       |
|        <-- DAL16 -|26  |____________|  35|- CLK -->          |
|          --> DMR -|27                  34|- CLK2 -->         |
|         --> MISS -|28                  33|- INIT <--         |
|         <-- PRDC -|29                  32|- CONT <--         |
|         NOT USED -|30                  31|- TEST2 <--        |
|                   |______________________|                   |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|Written by     Jonathan Bowen                                 |
|               Programming Research Group                     |
|               Oxford University Computing Laboratory         |
|               8-11 Keble Road                                |
|               Oxford OX1 3QD                                 |
|               England                                        |
|                                                              |
|               Tel +44-865-273840                             |
|                                                              |
|Created        May 1983                                       |
|Updated        April 1985                                     |
|Issue          1.1                Copyright (C) J.P.Bowen 1985|
----------------------------------------------------------------
[I interrupt this reference card to add these pin descriptions from the EK-KDJ1D-UG manual:]
INPUTS
------
RHALT	Receive halt, from console break or Qbus BHALT
LTC	Line Time Clock interrupt, vector 100
PE	parity error, causes ABORT, vector 114
PWRF	power fail, from Qbus BPOK, vector 24
IRQ0	Interrupt request 0, from Qbus BIRQ4 or either SLU, level 4
DV	data valid, latches DAL data input
DCOK	DC power OK, from Qbus BDCOK, causes powerup sequence to execute
RDMR	Receive DMA request, from Qbus BDMR
CONT	terminates a stretched cycle
XTAL(2)	crystal oscillator connections
INPUT/OUTPUT
------------
ABORT	asserted by J11 during first part of I/O cycle, or externally during stretched part of non I/O cycle
	internal: MMU error, vector 240
	internal: address error, vector 4
	external w/ PE, vector 114
	external w/ NXM, vector 4
DAL(16)	muxed address/data lines.
	first part of cycle:
		Bus read or write: address [15:0]
		GP read or write: 8 bit GP code
			000, read, maintenance register
			002, read, maintenance register
			214, write, negate INIT
			024, write, assert INIT
			100, write, ack BEVNT
			140, write, ack PWRF
		Interrupt Ack: 4 bit priority level
	second part of cycle: data
JDAL(6)	upper address bits
	first part of cycle: upper address
	second part of cycle: internal status
ALE	address latch enable, used to latch MAP, DAL, AIO, BS
STRB	asserted one clock after ALE
MAP	map enable
	first part of cycle: enable external I/O map (is this a Unibus thing?)
	second part of cycle: RDMR ack
SRUN	opcode is being decoded, wired to QBus AF1 for run indicator
AIO(4)	cycle type:
		0  bus word write
		3  bus byte write
		5  GP word write
		8  instruction stream demand-read
		9  data stream read
		10 read-modify-write, bus lock 
		11 read-modify-write, no bus lock
		12 instruction stream request-read (instruction prefetch, no effect if aborted)
		13 interrupt ack, vector read
		14 GP read
		15 non I/O, internal operatiom
BS(2)	bank select
	first part of cycle: type of device being addressed
		0 memory 0:17757777
		1 system registers 17777740:17777750
		2 external I/O device 17760000:17777777 except internal and system registers
		3 internal register, including PSW, PIRQ, CPU error. MMU, Hit/Miss
	second part of cycle: cache access information
CLK2	output of internal clock, same freq as xtal
SCTL	stretch control, asserted at start of stretched cycle, terminated by CONT 
BFCTL	buffer control, asserted when J11 is not driving DAL lines
The KDJ11-D/S does not use a cache or FPU, therefore the manual does not describe how the
DCJ11 interacts with those components.
[Back to Jonathan Bowen's cheat sheet]
----------------------------------------------------------------
|Mnemonic |Opcode|NZVC|Description               |Notes        |
|---------+------+----+--------------------------+-------------|
|ADCb d   |B055DD|****|Add Carry                 |d=d+C        |
|ADD  s,d |06SSDD|****|Add                       |d=s+d        |
|ASH  s,r |072RSS|****|Arithmetic Shift Combined |        (EIS)|
|ASLb d   |B063DD|****|Arithmetic Shift Left     |d=d*2        |
|ASRb d   |B062DD|****|Arithmetic Shift Right    |d=d/2        |
|BCC  a   |1030XX|----|Branch if Carry Clear     |If C=0       |
|BCS  a   |1034XX|----|Branch if Carry Set       |If C=1       |
|BEQ  a   |0014XX|----|Branch if Equal           |If Z=0       |
|BGE  a   |0020XX|----|Branch if Greater or Equal|If NxV=0     |
|BGT  a   |0030XX|----|Branch if Greater Than    |If Zv{NxV}=0 |
|BICb s,d |B4SSDD|**0-|Bit Clear                 |d=d&{~s}     |
|BISb s,d |B5SSDD|**0-|Bit Set (OR)              |d=dvs        |
|BITb s,d |B3SSDD|**0-|Bit Test (AND)            |d&s          |
|BHI  a   |1010XX|----|Branch if Higher          |If CvZ=0     |
|BHIS a   |1030XX|----|Branch if Higher or Same  |If C=0       |
|BLE  a   |0034XX|----|Branch if Less or Equal   |If Zv{NxV}=1 |
|BLT  a   |0024XX|----|Branch if Less Than       |If NxV=1     |
|BLO  a   |1034XX|----|Branch if Lower           |If C=1       |
|BLOS a   |1014XX|----|Branch if Lower or Same   |If CvZ=1     |
|BMI  a   |1004XX|----|Branch if Minus           |If N=1       |
|BNE  a   |0010XX|----|Branch if Not Equal       |If Z=1       |
|BPL  a   |1000XX|----|Branch if Plus            |If N=0       |
|BPT      |000003|----|Breakpoint Trap           |Vector at 14 |
|BR   a   |0004XX|----|Branch                    |PC=PC+2*XX   |
|BVC  a   |1020XX|----|Branch if Overflow Clear  |If V=0       |
|BVS  a   |1024XX|----|Branch if Overflow Set    |If V=1       |
|CALL d   |0047DD|----|Call subroutine           | (= JSR PC,d)|
|CCC      |000257|0000|Clear all Condition Codes |{C,N,V,Z}=0  |
|CLC      |000241|---0|Clear Carry               |C=0          |
|CLN      |000250|0---|Clear Negative            |N=0          |
|CLRb d   |B050DD|0100|Clear                     |d=0          |
|CLV      |000242|--0-|Clear Overflow            |V=0          |
|CLZ      |000244|-0--|Clear Zero                |Z=0          |
|CMPb s,d |B2SSDD|****|Compare                   |s-d          |
|COMb d   |B051DD|**01|Complement                |d=~d         |
|DECb d   |B053DD|***-|Decrement                 |d=d-1        |
|DIV  s,r |071RSS|****|Divide                    |r=r/s   (EIS)|
|EMT  t   |1040TT|----|Emulator Trap             |Vector at 30 |
|FADD r   |07500R|**00|Floating Add              |        (FIS)|
|FDIV r   |07503R|**00|Floating Divide           |        (FIS)|
|FMUL r   |07502R|**00|Floating Multiply         |        (FIS)|
|FSUB r   |07501R|**00|Floating Subtract         |        (FIS)|
|HALT     |000000|----|Halt                      |             |
|INCb d   |B052DD|***-|Increment                 |d=d+1        |
|IOT      |000004|----|Input/Output Trap         |Vector at 20 |
|JMP  d   |0001DD|----|Jump                      |PC=d         |
|JSR  r,d |004RDD|----|Jump to Subroutine        |r=PC,PC=d    |
|MARK n   |0064NN|----|Mark stack                |RTS aid      |
|MFPD s   |1065SS|**0-|Move From Previous Data   |             |
|MFPI s   |0065SS|**0-|Move From Previous Instr. |             |
|MOVb s,d |B1SSDD|**0-|Move                      |d=s          |
|MTPD d   |1066DD|**0-|Move To Previous Data     |             |
|MTPI d   |0066DD|**0-|Move To Previous Instr.   |             |
|MUL  s,r |070RSS|**0*|Multiply                  |r=r*s   (EIS)|
|NEGb d   |B054DD|****|Negate                    |d=-d         |
|NOP      |000240|----|No Operation              |             |
|RESET    |000005|----|Reset external bus        |             |
|RETURN   |000207|----|Return from subroutine    |   (= RTS PC)|
|ROLb d   |B061DD|****|Rotate Left               |d={C,d}<-    |
|RORb d   |B060DD|****|Rotate Right              |d=->{C,d}    |
|RTI      |000002|----|Return from Interrupt     |{PC,PS}=(SP)+|
|RTS  r   |00020R|----|Return from Subroutine    |PC=r,r=(SP)+ |
|RTT      |000006|----|Return from Trace trap    |No T trap    |
|SBCb d   |B056DD|****|Subtract Carry            |d=d-C        |
|SCC      |000277|1111|Set all Condition Codes   |{C,N,V,Z}=0  |
|SEC      |000261|---1|Set Carry                 |C=1          |
|SEN      |000270|1---|Set Negative              |N=1          |
|SEV      |000262|--1-|Set Overflow              |V=1          |
|SEZ      |000264|-1--|Set Zero                  |Z=1          |
|SOB  r,a |077RNN|----|Subtract One and Branch   |PC=PC-2*NN   |
|SPL  n   |00023N|----|Set Priority Level        |PS<7:5>=N    |
|SUB  s,d |16SSDD|****|Subtract                  |d=d-s        |
|SWAB d   |0003DD|**00|Swap Bytes                |             |
|SXT  d   |0067DD|-*0-|Sign Extend               |d=0 or -1    |
|TRAP t   |1044TT|----|Trap                      |Vector at 34 |
----------------------------------------------------------------
----------------------------------------------------------------
|Mnemonic |Opcode|NZVC|Description               |Notes        |
|---------+------+----+--------------------------+-------------|
|TSTb d   |B055DD|**00|Test                      |d            |
|WAIT     |000001|----|Wait for interrupt        |             |
|XOR  r,d |074RDD|**0-|Exclusive OR              |d=dxr        |
|---------+------+----+----------------------------------------|
|         |     B|    |0 for word, 1 for byte (1 bit)          |
|         |    DD|    |Destination field (6 bits)              |
|         |     N|    |Number (3 bits)                         |
|         |    NN|    |Number (6 bits)                         |
|         |     R|    |Register (3 bits, R0-5/SP/PC)           |
|         |    SS|    |Source field (6 bits)                   |
|         |    TT|    |Number (8 bits)                         |
|         |    XX|    |Offset (8 bits, -128 to +127)           |
|----------------+----+----------------------------------------|
| PSW            |-*01|Flag unaffected/affected/reset/set      |
|                |    |Current mode (Bits 15 to 14)            |
|                |    |Previous mode (Bits 13 to 12)           |
|                |    |General register set (Bit 11)           |
|                |    |Priority level (Bits 7 to 5)            |
| T              |    |Trace trap (Bit 4)                      |
| N              |N   |Negative (Bit 3)                        |
| Z              | Z  |Zero (Bit 2)                            |
| V              |  V |Overflow (Bit 1)                        |
| C              |   C|Carry (Bit 0)                           |
|---------------------+----------------------------------------|
| r                   |Register (mode 0)                       |
| (r)                 |Register deferred (mode 1)              |
| @r                  | ditto                                  |
| (r)+                |Auto-increment (mode 2)                 |
| @(r)+               |Auto-increment deferred (mode 3)        |
| -(r)                |Auto-decrement (mode 4)                 |
| @-(r)               |Auto-decrement deferred (mode 5)        |
| nn(r)               |Index (mode 6)                          |
| @nn(r)              |Index deferred (mode 7)                 |
| #nn                 |Immediate (mode 2, r=PC)                |
| @#nn                |Absolute (mode 3, r=PC)                 |
| nn                  |Relative (mode 6, r=PC)                 |
| @nn                 |Relative deferred (mode 7, r=PC)        |
|---------------------+----------------------------------------|
| Rn                  |General purpose Register (16-bit, n=0-5)|
| SP                  |Stack Pointer (16-bit, R6)              |
| PC                  |Program Counter (16-bit, R7)            |
| PS                  |Processor Status (16-bit)               |
|---------------------+----------------------------------------|
| a                   |Relative address                        |
| b                   |Blank or B for word or byte operand(s)  |
| d                   |Destination                             |
| n                   |Register number (0 to 5)                |
| nn                  |16-bit expression (0 to 65535)          |
| r                   |Register (Rn,SP,PC)                     |
| s                   |Source                                  |
| t                   |Trap number (0 to 255)                  |
| +   -               |Add/subtract                            |
| *   /               |Multiply/divide                         |
| ^                   |Exponent power                          |
| &   ~               |Logical AND/NOT                         |
| v   x               |Logical inclusive/exclusive OR          |
| <-  ->              |Rotate left/right                       |
| { }                 |Combination of operands                 |
| < : >               |Bit range                               |
|---------------------+----------------------------------------|
| DEC                 |Digital Equipment Corporation           |
| EIS                 |Extended fixed point Instruction Set    |
| FIS                 |Floating point Instruction Set          |
| PSW                 |Processor Status Word                   |
|---------------------+----------------------------------------|
| 000                 |Reserved vector                         |
| 004                 |Time-out/system error vector            |
| 010                 |Illegal and reserved instruction vector |
| 014                 |BPT instruction vector                  |
| 020                 |IOT instruction vector                  |
| 024                 |Power fail vector                       |
| 030                 |EMT instruction vector                  |
| 034                 |TRAP instruction vector                 |
| 060                 |Console input device vector             |
| 064                 |Console output device vector            |
| 100                 |External event line interrupt vector    |
| 160000-177776       |Device addresses                        |
----------------------------------------------------------------

(used by permission)

 

Last modified: December 31, 2009